Deterministic BIST for RNS Adders

Modulo 2 ÿ 1 adders as fast as n-bit 2’s complement adders have been recently proposed in the open literature. This makes a Residue Number System (RNS) adder with channels based on the moduli 2, 2 ÿ 1, and any other of the form 2 ÿ 1, with k < n, faster than RNS adders based on other moduli. In this paper, we formally derive a parametric, with respect to the adder size, test set, for parallel testing of the channels of an RNS adder based on moduli of the form 2; 2 ÿ 1; 2 ÿ 1; 2 ÿ 1; . . . ; with l < k < n. The derived test set is reusable; it can be used for any value of n; k; l; . . . , regardless of the implementation library used and is composed of n þ 2 test vectors. A test-per-clock BIST scheme is also proposed that applies the derived test vectors within n þ 2n cycles. Static CMOS implementations reveal that the proposed BIST offers 100 percent postcompaction fault coverage and an attractive combination of test time and implementation area compared to ROM and FSM-based deterministic BIST or LFSR-based pseudorandom BIST.